(VFetch stage
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I3
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I10
sVwid_order
p12
I10
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V001_MMU translation
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I2
sg8
g17
sVtag
p23
VVP_IP010_P001
p24
sVitem_list
p25
(dp26
sg12
I1
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_FRONTEND_F010_S001_I000
p34
sVdescription
p35
VThe Fetch stage asks the MMU to translate the requested address.
p36
sVpurpose
p37
VFRONTEND sub-system/functionality/Fetch stage
p38
sVverif_goals
p39
VExecute a program with virtual PC
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I-1
sVtest_type
p44
I-1
sVcov_method
p45
I-1
sVcores
p46
I16
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
a(V001
p57
g1
(g29
g3
Ntp58
Rp59
(dp60
g8
V001
p61
sg23
VVP_FRONTEND_F010_S001_I001
p62
sg35
VThe Fetch stage asks the MMU to translate the requested address.
p63
sg37
VFRONTEND sub-system/functionality/Fetch stage
p64
sg39
VCheck the translation does not impact execution time by executing Coremark in pphysical and virtual modes.
p65
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I16
sg47
g42
sg48
g42
sg49
(lp66
sg15
(lp67
sg52
(lp68
sg13
(dp69
g55
I0
ssbtp70
asVrfu_list_1
p71
(lp72
sg52
(lp73
sg13
(dp74
sbtp75
a(V002_Exceptions
p76
g1
(g18
g3
Ntp77
Rp78
(dp79
g22
I4
sg8
g76
sg23
VVP_IP010_P002
p80
sg25
(dp81
sg12
I2
sg15
(lp82
(V000
p83
g1
(g29
g3
Ntp84
Rp85
(dp86
g8
V000
p87
sg23
VVP_FRONTEND_F010_S002_I000
p88
sg35
VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults.
p89
sg37
VFRONTEND sub-system/functionality/Fetch stage
p90
sg39
VGenerate a bus error exception by UVM or by test (to be decided) and check that the exception address is fetched. Functional cov: a bus error exception occurs.
p91
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I8
sg47
g42
sg48
g42
sg49
(lp92
sg15
(lp93
sg52
(lp94
sg13
(dp95
g55
I0
ssbtp96
a(V002
p97
g1
(g29
g3
Ntp98
Rp99
(dp100
g8
V002
p101
sg23
VVP_FRONTEND_F010_S002_I002
p102
sg35
VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults.
p103
sg37
VFRONTEND sub-system/functionality/Fetch stage
p104
sg39
VGenerate an invalid access exception by UVM or by test (to be decided) and check that the exception address is fetched. Functional cov: an invalid access exception occurs.
p105
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I8
sg47
g42
sg48
g42
sg49
(lp106
sg15
(lp107
sg52
(lp108
sg13
(dp109
g55
I0
ssbtp110
a(V003
p111
g1
(g29
g3
Ntp112
Rp113
(dp114
g8
V003
p115
sg23
VVP_FRONTEND_F010_S002_I003
p116
sg35
VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults.
p117
sg37
VFRONTEND sub-system/functionality/Fetch stage
p118
sg39
VGenerate an instruction page faults and check that the exception is triggered
p119
sg41
g42
sg43
I-1
sg44
I-1
sg45
I-1
sg46
I16
sg47
g42
sg48
g42
sg49
(lp120
sg15
(lp121
sg52
(lp122
sg13
(dp123
g55
I0
ssbtp124
asg71
(lp125
sg52
(lp126
sg13
(dp127
sbtp128
asVrfu_list_0
p129
(lp130
sg71
(lp131
sVvptool_gitrev
p132
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p133
sVio_fmt_gitrev
p134
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p135
sVconfig_gitrev
p136
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p137
sVymlcfg_gitrev
p138
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p139
sbtp140
.